1. Field of the Invention
The present invention relates to telecommunication systems especially wireless systems, wireless transmitters and wireless receivers, especially those using the Bluetooth standard. The present invention also relates to semiconductor integrated circuits that implement a wireless receiver and/or a wireless transmitter especially those using the Bluetooth standard, as well as software for implementing the transmitter and/or receiver.
2. Technical Background
Version 2.0 +EDR of the Bluetooth standards introduces an Enhanced Data Rate (EDR) operation. The EDR standard is an improvement over the Basic Rate standard. New modulation schemes: π/4-DQPSK and 8DPSK, are proposed. The bandwidth of the channel is 1 MHz.
In the digital part of the receiver an SRRC filter is proposed which is matched with the SRRC filter used in transmitter. This filter behavior has been selected for Bluetooth EDR specifications to achieve a Raised Cosine (RC) filter in order to reduce the level of Intersymbol Interference (ISI). These matched filters result in a Raised Cosine Channel response. This channel, when given additional phase and amplitude compensation, will yield no ISI.
A Bluetooth transmitter is shown schematically in FIG. 1. The bits for transmission arrive at 2 Mbps or 3 Mbps and are coded in symbols “an” at 1 Msymbol per second. So the symbol time period T is 1 μs. The symbols are shaped with the SRRC and the modulated signal at digital level can be produced using any whole multiple of 1 MHz. For example, 13 MHz can be used as this is an available clock in a Bluetooth system. Finally a Digital to analog converter (DAC) is used to produce the analog modulated signal to be sent to the analog part of the transmitter.
A Bluetooth receiver has an analog front end and a digital part. At the Analog to Digital converter (ADC) in a Bluetooth receiver there are two simple possibilities for the sampling frequency: 13 MHz or 6.5 MHz. When operating at a sampling frequency of 6.5 MHz, theoretically the SRRC-receive filters (SRRC-Rx) could be matched to the SRRC-transmit filter (SRRC-Tx). However, after the SRRC-Rx filter, a sampled signal by 1 MHz frequency value is required as a digitized input for the demodulation block. The sampling frequency for the receiver has to be an integer multiple of the output frequency value of 1 MHz. Therefore, the implementation of the 6.5 MHz sampling frequency in the digital part of the receiver requires a preliminary block sampling at a whole multiple frequency of 1 MHz to obtain an equivalent digitized signal. This solution however requires generation of a sampling frequency at a whole multiple frequency of 1 MHz. The additional oscillator required to generate a whole multiple frequency of 1 MHz takes up chip area and increases power consumption. The alternative—sampling at 13 MHz—increases the complexity of the demodulator block, increases power consumption and cost.